HILLSBORO, OR -- (Marketwire) -- 11/10/09 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced Version 8.0 of its
ispLEVER® FPGA design tool suite, which includes many enhancements
for the design of high speed double data rate (DDR) interfaces for the
LatticeECP3(TM) FPGA family. These enhancements include automatic
interface code generation to increase design productivity and reduce coding
errors, as well as enhanced timing analysis that provides more transparency
to circuit timing details.
"Although our ECP3 FPGA family probably is best known for its low power and
SERDES capability, it also provides very advanced support for high
performance DDR interfaces. Designers can now use ispLEVER 8.0 software to
build and validate high speed, robust DDR interfaces more quickly," said
Mike Kendrick, Lattice's Manager of Software Product Planning.
Enhanced LatticeECP3 Support for High Speed DDR Interfaces
The IPexpress(TM) tool now can generate the HDL for the most appropriate
generic DDR interface based on user requirements such as direction, speed
and bus width. This HDL has been specifically designed and validated for
high performance, robust operation. For the ECP3 family, certain DDR
interfaces can now be implemented with much higher pin layout flexibility.
Since an important part of robust DDR interface operation is a clean
transfer between the IO and fabric clock domains, the Trace static timing
analysis report has been enhanced to include a "Timing Rule Check" section
that specifically analyzes these clock domain transfers. This is done
automatically and does not require users to define additional timing
constraints.
The IPexpress tool can now also optionally generate the complete
I/O-specific circuitry for proprietary DDR memory interfaces, allowing
designers to focus solely on the controller logic of their DDR1 and DDR2
DRAM interfaces.
Improved Runtime Performance
Continuous improvement and innovation in place and route algorithms enable
ispLEVER 8.0 software to complete large, congested designs 30% faster than
with the previous ispLEVER 7.2 SP2 release.
Enhanced Support for the Open Source LatticeMico32 Microprocessor Solution
Lattice continues to enhance and expand support for the innovative open
source 32-bit RISC LatticeMico32(TM) ecosystem. The GNU compiler (GCC) has
been upgraded to Version 4.3.0, which enables higher system performance and
more flexible code deployment options. The Tri-speed MAC IP can now be
interconnected into higher throughput configurations. The component
library now includes a Dual Port on-chip memory to enable high speed
information passing between Wishbone bus masters, and an enhanced SPI Flash
Controller allows both read and write access.
About the ispLEVER Design Tool Suite
The ispLEVER design tool suite is the flagship design environment for the
latest Lattice FPGA products. It provides a complete set of powerful tools
for all design tasks, including project management, IP integration, design
planning, place and route, in-system logic analysis and more. Version 8.0
of the ispLEVER software adds support for Red Hat Enterprise Linux 5.3.
Synopsys' Synplify Pro advanced FPGA synthesis is included for all
operating systems supported, and Aldec's Active-HDL Lattice Edition
simulator is included for Windows. The ispLEVER 8.0 software also comes
bundled with the LatticeMico32 System and ispLEVER Classic, as well as with
the PAC-Designer® tools that target mixed signal design. The ispLEVER
tool suite is provided on DVD for Windows, UNIX or Linux platforms.
Third Party Tool Support
In addition to the tool support for Lattice devices provided by the OEM
versions of Synplify Pro and Active-HDL, which are included in the ispLEVER
tool suite, Lattice devices are also supported by the full versions of
Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE
and Precision RTL synthesis also support the latest Lattice devices, such
as the LatticeECP3 family.
Pricing and Availability
The ispLEVER 8.0 tool suite for Windows, LINUX and UNIX users is available
immediately without charge for customers with active design tool
maintenance contracts. Pricing for the full ispLEVER design tool suite
starts at $1,295 for the Windows version.
Lattice Semiconductor Corporation, Lattice (& design), L (& design),
ispLEVER, LatticeECP3, IPexpress, LatticeMico32, PAC-Designer and specific
product designations are either registered trademarks or trademarks of
Lattice Semiconductor Corporation or its subsidiaries in the United States
and/or other countries.
GENERAL NOTICE: Other product names used in this publication are for
identification purposes only and may be trademarks of their respective
holders.
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