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SYS-CON MEDIA Authors: Liz McMillan, Pat Romanski, Carmen Gonzalez, Kevin Jackson, Peter Silva

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Jasper Launches Sequential Equivalence Checking App to Formally Verify the Functional Equivalence of RTL Implementations

New App Compares Two RTL Implementations Orders of Magnitude Faster Than Simulation or Other Sequential Equivalence Checking Tools

MOUNTAIN VIEW, CA -- (Marketwired) -- 03/31/14 --


Highlights:

  • Achieve 10x faster sequential equivalence checking than other such tools on the market
  • Eliminate the need for weeks of simulation regressions after even minor design changes
  • Perform sequential equivalence checking on both large sub-system blocks and complete SoCs
  • Have confidence in design sign-off with technology that proves exhaustively that two designs expressed in RTL exhibit the exact same behavior at sequential design points
  • Simplify and speed verification environment setup, comparative analysis and debug

Jasper Design Automation, the leading provider of verification solutions based on state-of-the-art formal technology, has announced the availability of its new JasperGold® Sequential Equivalence Checking App (SEC App). The new SEC App enables designers to exhaustively verify the sequential functional equivalence of RTL implementations, ensuring that they function identically at sequential design points, -- and 10x faster than competing tools.

SOC designers often make changes to RTL that may not be purely functional. Low power optimization, using structures such as clock gating, power gating and power domain partitioning is a common motivation for such changes. Other changes might be motivated by the need to optimize performance or insert ECOs into the design. Faced with two versions of the RTL design, the designer needs to verify that the new RTL is sequentially equivalent to the previous RTL. Moreover, this task must be repeated for every change, however small. Comparing the two versions of the RTL in simulation can take weeks of regression runs. In addition, because simulation is non-exhaustive by nature the results are far from certain. Traditional equivalence checking tools can be used for this task but, so far, the market solutions have been too slow and too limited by the size of the designs that they can handle. The SEC App can accept large sub-system blocks as well as complete SOCs and compare the two versions of the RTL orders of magnitude faster than simulation.

"We have been using Jasper's Sequential Equivalence Checking App, for a specific verification task that checks the remapping of a complete set of memory instances, with great success," commented Philippe Magarshack, Executive VP & GM, Design Enablement & Services at STMicroelectronics. "In our GPU designs, we have systematically replaced the incoming memory blocks of IP modules with a different memory architecture, specifically optimized for our 28nm FD-SOI Low-Power Platform. The Jasper SEC App allowed us to very smoothly verify that this substitution did not alter the behavior of our design, giving us strong confidence in the resulting optimized GPU micro-architecture. We can now run exhaustive checks in hours vs. the weeks it used to take us to run a non-exhaustive simulation for this important use case."

"The SEC App leverages a combination of algorithmic techniques, new optimized engines, and a customized GUI -- all specially targeted for equivalence checking challenges," said Rajeev Ranjan, CTO of Jasper. "Our customers have found that this tailor-made approach delivers results considerably superior to those from simulation-based methods or general purpose formal tools. For example, another customer reported that with only one machine, Jasper's SEC app was able to simultaneously verify timing fixes, chicken bits, clock gating validation, and power optimizations in only 45 minutes. This performance completely blew away their prior simulation-based regression flow that took five days to run on a whole rack of computers."

Streamlining Sequential Equivalence Checking
The JasperGold SEC App's optimized formal engine executes up to 10x faster than the application of other sequential equivalence checking solutions, and orders of magnitude faster than simulation runs performing a similar task. It also enables the App to handle difficult multi-value logic cases, such as "non-resettable flops," "$isunknown," "Verilog 'X' values" and "dangling signals." The SEC App can perform non-cycle accurate verification using temporal and functional mapping. Equipped with this "verification context" technology, it is possible to apply the SEC App to formally compare a high level model or reference model against its RTL implementation. The two models may not necessarily match every cycle, or require certain logical expressions to match.

The App's model setup wizard simplifies and speeds verification environment setup, and is complemented by an optimized debug GUI that shows the "specification" side-by-side with the "implementation," simplifying comparative analysis and debug. The wizard supports mixed languages and the Unified Power Format (UPF). In addition to the App's ability to formally verify the equivalence of RTL implementations, it can also deal with RTL engineering change orders (ECOs) quickly and efficiently to make sure any changes do not affect the intended behavior of the design.

Availability
The new Sequential Equivalence Checking App is available now. For pricing and sales inquiries, please contact [email protected].

To learn more about the JasperGold Sequential Equivalence Checking App, check out the following videos.

About JasperGold Apps
JasperGold Apps are built on a single platform that combines multiple formal-based solutions and leverages a common shared database and user interface. The Apps architecture enables sharing of design and verification data for each design under test (DUT) between Apps for increased consistency and productivity. The Apps architecture supports deployment of multiple Apps simultaneously as well as multiple invocations of the same App for improved throughput and performance.

The Apps architecture is extensible such that customers can take advantage of future Apps that will address emerging design and verification needs. The design and verification challenges that customers have addressed by creating flows using our formal technology have been the inspiration for several Apps. Customers will be able to continue to leverage the powerful and highly programmable platform in JasperGold to develop their customized flows.

About Jasper Design Automation
Jasper Design Automation delivers industry-leading software solutions for semiconductor design, verification, and Intellectual Property (IP) reuse, based on state-of-the-art formal technology. Customers include worldwide leaders in the wireless, consumer, computing, and networking electronics industries. Jasper technology has been an essential part of 150 plus successful chip deployments. Headquartered in Mountain View, California, the company is privately held, with offices and distributors in North America, South America, Europe, Israel, and Asia. Visit www.jasper-da.com to reduce risks, increase design, verification and reuse productivity and accelerate time to market.

Jasper Design Automation, the Jasper Design Automation logo, and JasperGold are trademarks or registered trademarks of Jasper Design Automation, Inc. All other trademarks mentioned are the property of their respective companies.

Contact:
Rob van Blommestein
650-966-0234 p
Email Contact

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