|By Marketwired .||
|June 2, 2014 10:00 AM EDT||
SAN FRANCISCO, CA -- (Marketwired) -- 06/02/14 -- The who's who of the chip design community will be in San Francisco this week for DAC, and new ideas, trends and technologies will be the talk of the show. Plunify, provider of a groundbreaking FPGA design application, will be on hand to join the conversations and offer a solution to some of the biggest challenges faced by FPGA designers today: meeting timing, reducing area and lowering power. At the show, Plunify will debut its new InTime software, which harnesses big data analytics to solve FPGA timing and optimization problems through machine learning -- without modifying code.
Used as a plugin to major FPGA tools, InTime is able to analyze an FPGA design and determine optimized strategies for synthesis and place-and-route. These strategies are derived from correlations between the design structure, types of FPGA resources used and the design constraints. InTime guides the design towards the specified timing, area or power performance goals. The sheer complexity and volume of data generated for every FPGA design makes it impractical for designers to analyze that data by hand, but InTime uses statistical methods and machine learning to draw insights from the data that can improve the quality of results. Additionally, InTime harnesses unused compute power to run builds -- and actively learns from build results to improve them over time.
According to Kirvy Teo, COO for Plunify, "InTime is incredibly intelligent -- InTime learns from previous build results and the more builds it does, the better the results become. InTime has the potential to be truly life-changing for FPGA designers -- enabling them to get better, faster results from the same FPGA software, without modifying their designs."
See for yourself -- Plunify invites DAC attendees to visit them at booth #209C on the show floor to get a firsthand look at InTime. To learn more, please visit www.Plunify.com, like them on Facebook or follow the company on Twitter.
Solutions from Plunify Pte. Ltd. enable semiconductor chip designers to shorten product time-to-market and reduce development costs -- with no disruption to existing workflows. The company's EDAxtend cloud platform and InTime timing closure tool help electronics companies meet FPGA design performance targets and significantly reduce their products' time to market. For more on Plunify's products, please visit www.plunify.com
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Lages & Associates